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| QST108 Capacitive touch sensor device 8 keys with individual key state outputs or I2C interface Not For New Design Features Patented charge-transfer design Up to 8 independent QTouchTM keys supported Individual key state outputs or I2C interface Fully "debounced" results Patented AKSTM Adjacent Key Suppression Self-calibration and auto drift compensation Spread-spectrum bursts to reduce EMI Up to 5 general-purpose outputs ECOPACK(R) (RoHS compliant) package LQFP32 (7x7 mm) Description The QST108 is the ideal solution for the design of capacitive touch sensing user interfaces. Touch-sensitive controls are increasingly replacing electromechanical switches in home appliances, consumer and mobile electronics, and in computers and peripherals. Capacitive touch controls allow designers to create stylish, functional, and economical designs which are highly valued by consumers, often at lower cost than the electromechanical solutions they replace. The QST108 QTouchTM sensor IC is a pure digital solution based on Quantum's patented chargetransfer (QProxTM) capacitive technology. QTouchTM and QProxTM are trademarks of the Quantum Research Group. Applications This device specifically targets human interfaces and front panels for a wide range of applications such as PC peripherals, home entertainment systems, gaming devices, lighting and appliance controls, remote controls, etc. QST devices are designed to replace mechanical switching/control devices and the reduced number of moving parts in the end product provides the following advantages: Lower customer service costs Reduced manufacturing costs Increased product lifetime Device summary Table 1. Order codes Feature QST108KT6 Operating supply voltage Supported interfaces Operating temperature Package 2.4 to 5.5 V Individual key state outputs or I2C Interface -40 to +85 C LQFP32 (7x7 mm) July 2008 Rev 5 1/51 www.st.com 1 This is information on a product still in production but not recommended for new designs. Contents QST108 Contents 1 2 3 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 QST touch sensing technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Spread-spectrum operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Faulty and unused keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Detection threshold levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Detection integrator filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Self-calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Fast positive recalibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Forced key recalibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Max On-Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Drift compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Adjacent key suppression (AKSTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 Device operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 4.2 4.3 4.4 4.5 Reset and power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Burst operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Stand-alone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5.1 4.5.2 4.5.3 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 KOUT outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Option descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 General-purpose outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 IRQ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Communication packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 I2C address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.6 I2C mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.6.1 4.6.2 4.6.3 4.6.4 4.6.5 4.7 Supported commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2/51 QST108 Contents 5 Design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 5.2 CS sense capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Sensitivity tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2.1 5.2.2 5.2.3 Increasing sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Decreasing sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Key balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3 5.4 5.5 5.6 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Crosstalk precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PCB layout and construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.2 6.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3.1 6.3.2 6.3.3 Functional EMS (electro magnetic susceptibility) . . . . . . . . . . . . . . . . . 32 Electro magnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 33 6.4 6.5 6.6 6.7 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Capacitive sensing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 KOUTn/OPTn/GPOn pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.7.1 6.7.2 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Output pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.8 6.9 RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 I2C control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.1 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8 9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Device revision information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3/51 Contents QST108 9.1 9.2 Device revision identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Device revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.2.1 9.2.2 Revision 2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Revision 2.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4/51 QST108 Device overview 1 Device overview The QST108 capacitive touch sensor IC is a pure digital solution based on Quantum's patented charge-transfer (QProxTM) capacitive technology. This technology allows users to create simple touch panel sensing electrode interfaces for conventional or flexible printed circuit boards (PCB/FPCB). Sensing electrodes are part of the PCB layout (copper pattern or printed conductive ink) and may be used in various shapes (circle, rectangular, etc.). By implementing the QProxTM charge-transfer algorithm, the QST108 detects finger presence (human touch) near electrodes behind a dielectric (glass, plastic, wood, etc.). Only one external sampling capacitor by channel is used in the measuring circuitry to control the detection. QST technology also incorporates advanced processing techniques such as drift compensation, auto-calibration, noise filtering, and Quantum's patented Adjacent Key SuppressionTM (AKSTM) to ensure maximum usability and control integrity. In order to meet environmental requirements, ST offers this device in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 5/51 Pin description QST108 2 Pin description Figure 1. 32-pin package pinout GPO4/KOUT4/OPT4 (HS) GPO5/KOUT5/OPT5 (HS) IRQ/KOUT6/OPT6 (HS) I2C_SDA/KOUT71) (HS) I2C_SCL/KOUT81) (HS) RESET NC VDD_1 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 QST108KT6 20 19 18 17 9 10 11 12 13 14 15 16 GPO3/OPT3/KOUT3 (HS) GPO2/OPT2/KOUT2 (HS) GPO1/OPT1/KOUT1 (HS) SNSK_SCK8 SNS_SCK8 SNSK_SCK7 SNS_SCK7 SNSK_SCK6 SNS_SCK6 SNSK_SCK5 SNS_SCK5 SNSK_SCK4 SNS_SCK4 SNSK_SCK3 SNS_SCK3 SNSK_SCK2 (HS) 20 mA high sink capability (on N-buffer only) 1. An external pull-up is required on these pins. Table 2. Pin 1 Device pin description Pin name Type (1) PP (HS) Stand-alone mode function Key 4 output / BCD output 4 and MOD_0 option resistor Key 5 output and MOD_1 option resistor Key 6 output and OM_0 option resistor Key 7 output Key 8 output I2C mode function If unused GPO4/OPT4/KOUT4 (2) 2 GPO5/OPT5/KOUT5 (2) PP (HS) VSS_1 VSS_2 VSS_3 VSS_4 VDD_2 SNS_SCK1 SNSK_SCK1 SNS_SCK2 General purpose output 4 Option and IC address bit 2 resistor option resistor Open or General purpose output 5 option resistor Interrupt line (active low) Open or option resistor Open Open I2C serial data I2C serial clock 3 OPT6/KOUT6/IRQ (2) PP/OD (HS) TOD (HS) TOD (HS) 4 5 KOUT7/I2C_SDA(3) KOUT8/I2C_SCL(3) 6/51 QST108 Table 2. Pin 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pin description Device pin description (continued) Pin name Type (1) BD Stand-alone mode function Reset (active low) Not connected S S S S S S SNS SNS SNS SNS SNS SNS SNS SNS SNS SNS SNS SNS SNS SNS SNS SNS PP (HS) Supply voltage Ground voltage Ground voltage Ground voltage Ground voltage Supply voltage Key 1 sense pin to Cs Key 1 sense pin to Cs/Rs Key 2 sense pin to Cs Key 2 sense pin to Cs/Rs Key 3 sense pin to Cs Key 3 sense pin to Cs/Rs Key 4 sense pin to Cs Key 4 sense pin to Cs/Rs Key 5 sense pin to Cs Key 5 sense pin to Cs/Rs Key 6 sense pin to Cs Key 6 sense pin to Cs/Rs Key 7 sense pin to Cs Key 7 sense pin to Cs/Rs Key 8 sense pin to Cs Key 8 sense pin to Cs/Rs Key 1 output / BCD output 1 and MODE option resistor Key 2 output / BCD output 2 and AKS option resistor Key 3 output / BCD output 3 and LP option resistor Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open General purpose output 1 Option and MODE option resistor resistor General purpose output 2 Option and I2C address bit 0 resistor option resistor General purpose output 3 Option and I2C address bit 1 resistor option resistor I2C mode function If unused 10nF capacitor to ground RESET NC VDD_1 VSS_1 VSS_2 VSS_3 VSS_4 VDD_2 SNS_SCK1 SNSK_SCK1 SNS_SCK2 SNSK_SCK2 SNS_SCK3 SNSK_SCK3 SNS_SCK4 SNSK_SCK4 SNS_SCK5 SNSK_SCK5 SNS_SCK6 SNSK_SCK6 SNS_SCK7 SNSK_SCK7 SNS_SCK8 SNSK_SCK8 GPO1/OPT1/KOUT1 (2) 31 GPO2/OPT2/KOUT2 (2) PP (HS) 32 GPO3/OPT3/KOUT3 (2) PP (HS) 1. S: supply pin, BD: bidirectional pin, SNS: capacitive sensing pin, PP: Output push-pull, OD: Output open-drain, TOD: Output true open-drain and HS: 20mA high sink capability (on N-buffer only) 2. During the reset phase, these pins are floating and their state depends on the option resistor. 3. An external pull-up is required on these pins. 7/51 QST touch sensing technology QST108 3 3.1 QST touch sensing technology Functional description QST devices employ bursts of charge-transfer cycles to acquire signals. Burst mode permits low power operation, dramatically reduces RF emissions, lowers susceptibility to RF fields, and yet permits excellent speed. Signals are processed using algorithms pioneered by Quantum which are specifically designed to provide reliable, trouble-free operation over the life of the product. The QST switches and charge measurement hardware functions are all internal to the device. An external CS capacitor accumulates the charge from sense-plate CX, which is then measured. Larger values of CX cause the charge transferred into CS to rise more rapidly, reducing available resolution. As a minimum resolution is required for proper operation, this can result in dramatically reduced gain. Larger values of CS reduce the rise of differential voltage across it, increasing available resolution by permitting longer QST bursts. The value of CS can thus be increased to allow larger values of CX to be tolerated. The device is responsive to both CX and CS, and changes in either can result in substantial changes in sensor gain. Figure 2. QTouchTM measuring circuitry CT (~5 pF) Serial resistor RS (10 k) SNSK_SCKn Earth SNS_SCKn Sense capacitor CS (a few nF) Cx (~20 pF) Ai12569 3.2 Spread-spectrum operation The bursts operate over a spread of frequencies, so that external fields will have minimal effect on key operation and emissions are very weak. Spread-spectrum operation works with the Detection Integrator mechanism (DI) to dramatically reduce the probability of false detection due to noise. 8/51 QST108 QST touch sensing technology 3.3 Faulty and unused keys Any sensing channel that does not have its sense capacitor (CS) fitted is assumed to be either faulty or unused. This channel takes no further part in operation unless a Mastercommanded recalibration operation shows it to have an in-range burst count again. Faulty, unused or disabled keys are still bursted but not processed to avoid modifying the sensitivity of active keys. This is important for sensing channels that have an open or short circuit fault across CS. Such channels would otherwise cause very long acquire bursts, and in consequence would slow the operation of the entire QST device. To optimize touch response time and device power consumption, if some keys are not used, we recommend to try suppressing the ones which belong to the same burst. Bursts which do not have any keys implemented will then not be processed. 3.4 Detection threshold levels The key capacitance change induced by the presence of a finger is sensed by the variation in the number of charge transfer pulses to load the capacitor. The difference in the pulse count number is compared to a threshold in order to detect the key as pressed or not. Two different thresholds, one for detection and one for the end of detection, create an hysteresis in order to prevent erratic behavior. The default threshold levels and hysteresis values are described in Section 6.6: Capacitive sensing characteristics on page 35. 3.5 Detection integrator filter The Detection Integrator (DI) filter mechanism works together with spread spectrum operation to dramatically reduce the effects of noise on key states. The DI mechanism requires a specified number of measurements that qualify as detections (and these must occur in a row) or the detection will not be reported. In a similar manner, the end of a touch (loss of signal) also has to be confirmed over several measurements. It is called the End of Detection Integrator (EDI). This process acts as a type of "debounce" mechanism against noise. The default DI and EDI values for confirming start of touch and end of touch are described in Section 6.6: Capacitive sensing characteristics on page 35. 9/51 QST touch sensing technology QST108 Figure 3 shows an example of detection with DI=2 and EDI=2 meaning 3 consecutive samples are necessary to trigger the key detection or end of detection Figure 3. Detection signals Reference count Reference + EofDeTh Burst count Hysteresis Reference + DeTh Key Detection signal Time = Sampling point 3.6 Self-calibration On power-up, all keys are self-calibrated to provide reliable operation under almost any conditions. The calibration phase is used to compute a reference value per key which is then used by the process determining if a key is touched or not. The reference is an average of 8 single acquisitions. As a result, the calibration time of the system can be simply calculated using the following formula: tCAL = 8 * Burst_Period. The methodology used to measure the burst period is described in application note AN2547. For a maximum calibration duration (tCAL), please refer to Section 6.6: Capacitive sensing characteristics on page 35. 3.7 Fast positive recalibration The device autorecalibrates a key when its signal reflects a decrease in capacitance higher than a fixed threshold (PosRecalTh) for a defined number of acquisitions (PosRecalI). 3.8 Forced key recalibration A recalibration of the device may be issued at any time by sending to the QST device the appropriate I2C command or by tying the RESET pin to ground. It is possible to recalibrate independently any individual key using an I2C command. 10/51 QST108 QST touch sensing technology 3.9 Max On-Duration The device can time out and automatically recalibrate each key independently after a fixed duration of continuous touch detection. This prevents the keys from becoming `stuck on' due to foreign objects or other sudden influences. This is known as the Max On-Duration feature. After recalibration, the key will continue to operate normally, even if partially or fully obstructed. Max On-Duration works independently per channel: a timeout on one channel has no effect on another channel. Infinite timeout is useful in applications where a prolonged detection can occur and where the output must reflect the detection no matter how long. In infinite timeout mode, the designer should take care to ensure that drift in CS, CX, and VDD do not cause the device to remain "stuck on" inadvertently even when the touching object is removed from the sense field. Timeout durations are not accurate and can vary substantially depending on VDD and temperature values, and should not be relied upon for critical functions. 3.10 Drift compensation Signal drift can occur because of changes in CX, CS, and VDD over time. Depending on the CS type and quality, the signal may vary substantially with temperature and veiling. If keys are subject to extremes of temperature or humidity, the signal can also drift. It is crucial that drift be compensated, otherwise false detections, non detections, and sensitivity shifts will follow. Drift compensation slowly corrects the reference level of each key while no detection is in effect. The rate of reference adjustment must be performed slowly or else legitimate detections can also be ignored. The device compensates drift on each channel independently using a maximum compensation rate to the reference level. Once a touch is sensed, the drift compensation mechanism ceases since the signal is legitimately high, and therefore should not cause the reference level to change. The signal drift compensation is "asymmetric": the reference level compensates drift in one direction faster than it does in the other. Specifically, it compensates faster for increasing signals than for decreasing signals. Decreasing signals should not be compensated for quickly, since an approaching finger could be compensated for partially or entirely while approaching the sense electrode. However, an obstruction over the sense pad, for which the sensor has already made full allowance, could suddenly be removed leaving the sensor with an artificially elevated reference level and thus become insensitive to touch. In this latter case, the sensor will compensate for the object's removal very quickly, usually in only a few seconds. Caution: When only one key is enabled or if keys are very close together, the common drift compensation must be disabled or its rate must be reduced to ensure correct device operation. 11/51 QST touch sensing technology QST108 Figure 4 illustrates an example of the drift compensation algorithm following a temperature change. Figure 4. Drift compensation example Reference Count + PosRelTh Temperature Change Reference Count Burst count Reference + DeTh Drift Compensation Time 3.11 Adjacent key suppression (AKSTM) Adjacent key suppression (AKSTM) is a Quantum-patented feature which prevents multiple keys from responding to a single touch. This can happen with closely spaced keys, or a scroll wheel that has buttons very near it. The QST108 supports two AKS modes: Locking AKS Once a key is considered as "touched", all other keys are locked in an untouched state. To unlock these keys, the touched key must return to an untouched state. Then, the key having the lowest key ID number is declared as the "touched" one. Unlocking AKS On each acquisition, the signal strengths from each key are compared and the key with the highest signal level is declared as the "touched" one. In I2C mode, up to 8 AKS groups can be specified. Note: All keys belonging to the same AKS group must have the same AKS mode. 12/51 QST108 Device operating modes 4 4.1 Device operating modes Reset and power-up At power-up, the device configures itself according to the pull-up or pull-down option resistors present on pins OPT1 to OPT6. The device start-up and configuration may take up to tSetup. When the power is established, it is possible to force a new device configuration by applying a negative pulse on the RESET pin. The RESET pin is a bidirectional pin with an internal pull-up. The line is forced low when the device resets itself (through an IC command, for example). A 10nF capacitor is recommended on the RESET pin to ensure reliable start-up and noise immunity. 4.2 Burst operation The device operates in "Burst" mode. Each key touch is acquired using a burst of chargetransfer sensing pulses whose count varies depending on the value of the sense capacitor CS and the load capacitance CX. Key touches are acquired using two successive bursts of pulses: Burst A: Keys 1, 2, 3, and 4 Burst B: Keys 5, 6, 7, and 8 Bursts always operate in an A-B sequence. If Keys 5 to 8 are not implemented, the QST device will not perform the Burst B to improve the response time and reduce the power consumption when in Low Power (LP) mode. In Low Power mode, the device sleeps in an ultra-low current state between bursts to conserve power. 4.3 Low power mode In order to reduce the device power consumption, the QST family include scalable low power modes. Standard low power mode When the device is in standard low power mode, a window with very low power consumption is inserted between the acquisition of the last active key and the following acquisition of the first active key. This window duration is programmable as the 'sleep duration time'. Note that the sleep window insertion is cancelled in the following conditions: - - If a change is detected on a key, in order to speed up the DI process, the sleep window insertion is skipped until the end of the DI process. In I2C mode, when a key change is actually detected and reported with a negative pulse on the IRQ pin. In this case, the low power mode is disabled until a command is received from the host. Inside an I2C command, between the Write and the Read I2C frames, the sleep period is skipped. - 13/51 Device operating modes QST108 Free run in detect The behavior in this mode is the same as in the standard low power mode except that the sleep window insertion is always skipped if any of the active keys is detected as touched. This is useful to improve the wheel response time. Deep Sleep mode In Deep Sleep mode, the device enters a very low power mode indefinitely. The device resumes its operations after receiving an I2C frame with any address or a reset. Caution: If an I2C frame is received while in Sleep or Deep Sleep mode, the device wakes up but does not acknowledge the frame (even if it has an I2C frame with the device address). The host must therefore send again the frame until it is taken in account and acknowledged. 4.4 Mode selection The device options are configured by connecting pull-up or pull-down resistors on OPTn pins. The device operating mode is selected using option pin 1 (OPT1) while the device settings are configured using option pins OPT2 to OPT6 (Table 3). Option pins are sampled at power-up and after a reset. To fit most applications, the QST108 device offers two different operating modes: Stand-alone mode This mode allows the user to simply replace existing mechanical switches with a capacitive sensing solution. It is designed for maximum flexibility and can accommodate most popular sensing requirements via option resistors (AKS, Low power, Max On-Duration and output modes). In this mode, the 8 output pins reflect the status of the 8 sensing channels. I2C mode In this mode, which is the most open one, the device is driven using the I2C interface. To avoid polling, the QST device features an output interrupt pin (IRQ). The IRQ line reports all key changes to the Master device. The QST (Slave) device can drive up to five general-purpose outputs. Table 3. Operating modes Option resistor function OPT1: Mode selection OPT2 Pin OPT1 is high at start-up Stand-alone mode Pin OPT1 is low at start-up I2C mode AKS ADD0 OPT3 LP ADD1 OPT4 OPT5 OPT6 OM MOD_0 MOD_1 ADD2 Unused Unused 14/51 QST108 Device operating modes 4.5 Stand-alone mode This mode allows the user to simply replace existing mechanical switch interface with a capacitive sensing solution. It is designed for maximum flexibility and can accommodate most popular sensing requirements via option resistors (see Figure 5). 4.5.1 Main features Pins KOUT1 to KOUT8 directly reflect the state of keys Selectable global adjacent key suppression (AKSTM) Selectable sleep duration Selectable Max On-Duration values Selectable BCD mode 15/51 Device operating modes Figure 5. Stand-alone mode typical schematic VDD VUNREG 4.7F 2.4~5.5V Volt. Reg. 4.7F 100nF 100nF QST108 8 13 Keep these parts close to IC RS8 Key8 10k 29 VDD_1 VDD_2 RESET 6 SNSK_SCK8 SNS_SCK8 SNSK_SCK7 SNS_SCK7 SNSK_SCK6 SNS_SCK6 SNSK_SCK5 SNS_SCK5 SNSK_SCK4 SNS_SCK4 SNSK_SCK3 SNS_SCK3 SNSK_SCK2 SNS_SCK2 To Host 10nF CS8 28 RS7 Key7 10k 27 VDD VDD CS7 26 RS6 Key6 10k 10k 10k 25 CS6 24 KOUT8 KOUT7 OM/KOUT6 5 KOUT8 KOUT7 KOUT6 VDD VSS KOUT5 VDD VSS KOUT4 VDD BinaryVSS coded KOUT3 Output Mode VDD VSS KOUT2 VDD VSS KOUT1 VDD RS5 Key5 10k 23 4 CS5 22 3 RS4 Key4 10k 21 1M CS4 20 MOD_1/KOUT5 2 RS3 Key3 10k 19 1M CS3 MOD_0/KOUT4 1 18 1M RS2 Key2 10k 17 LP/KOUT3 32 CS2 16 1M RS1 Key1 10k AKS/KOUT2 15 31 SNSK_SCK1 SNS_SCK1 VSS_1 9 1M CS1 14 MODE/KOUT1 VSS_3 11 30 VSS_2 10 VSS_4 12 1M Ai12560 4.5.2 KOUT outputs KOUTn outputs directly reflect the state of keys. These pins are push-pull outputs except for pins KOUT7 and KOUT8 which are true open-drain outputs. Under RESET, these pins are floating and their state depends on the option resistors. Pins KOUTn are active high meaning that when a key is "touched", the corresponding KOUT pin outputs a `1'. 16/51 QST108 Device operating modes 4.5.3 Option descriptions Adjacent key suppression (AKSTM) The QST108 features an adjacent key suppression (AKSTM) function. This function is enabled using the AKS option resistor (OPT2) in standard output mode as described in Table 4. In BCD output mode, the AKS function is always enabled, regardless of the option resistor configuration. Table 4. AKS truth table Description Disabled Global locking AKS on all available keys OPT2/AKS VSS VDD Low Power mode option This option resistor (OPT3) selects whether the device is always sensing the keys or if a low power consumption phase is introduced between bursts as described in Table 5. In Low Power mode, a very low consumption (sleep) phase of 100ms is inserted between the Group B burst and the Group A burst. This significantly reduces the overall consumption of the device. Sleep duration is not accurate and can vary substantially depending on VDD and temperature values. Note: In Low Power mode, the response time is increased. Table 5. Low power (LP) mode truth table Description Free running mode 100ms sleep duration OPT3/LP VSS VDD Max On-Duration There are four recalibration timing options ("Max On-Duration"). The recalibration option resistors (OPT4 and OPT5) control how long it takes for a continuous detection to trigger a recalibration on a key as described in Table 6. When such an event occurs, only the "stuck" key is recalibrated. Table 6. Max On-Duration (MOD) truth table Description Infinite 60s 20s 10s OPT4/MOD_0 OPT5/MOD_1 VSS VSS VDD VDD VSS VDD VSS VDD 17/51 Device operating modes QST108 Output mode option The QST108 offers several outputs mode to fit any existing application. Table 7. OPT6/OM VSS VDD Output mode (OM) truth table Description Individual key state output mode: One output per sensing channel BCD output mode: Binary-coded touched key number (see Table 8)(1) 1. In BCD mode, the AKS function must be enabled. Table 8. Binary code truth table Description All released Key 1 pressed Key 2 pressed Key 3 pressed Key 4 pressed Key 5 pressed Key 6 pressed Key 7 pressed Key 8 pressed Not used KOUT4 KOUT3 KOUT2 KOUT1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 Other 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 18/51 QST108 Device operating modes 4.6 I2C mode The I2C mode offers the largest configurability and functionality of the QST108. 4.6.1 Main features 5 general-purpose outputs Configuration of up to 8 AKS groups Additional low power modes Accessible internal capacitive sensing parameters Continuous range of Max On-Duration Figure 6. I2C mode typical schematic VDD VUNREG 2.4~5.5V Volt. Reg. 100nF 4.7F 4.7F 100nF 8 13 VDD VDD_1 Keep these parts close to IC VDD_2 RS8 Key8 10k 4.7k 2.7k CS8 28 27 RS7 Key7 10k SNS_SCK8 SNSK_SCK7 SNS_SCK7 SNSK_SCK6 SNS_SCK6 SNSK_SCK5 SNS_SCK5 SNSK_SCK4 SNS_SCK4 SNSK_SCK3 SNS_SCK3 SNSK_SCK2 ADD1/GPO3 ADD2/GPO4 GPO5 I2C_SCL I2C_SDA IRQ RESET 5 4 3 6 2.7k 29 SNSK_SCK8 CS7 26 25 RS6 Key6 10k To Host MCU To Host 10nF CS6 24 23 RS5 Key5 10k CS5 22 21 2 RS4 Key4 10k GPO5 CS4 20 19 1 RS3 Key3 10k CS3 18 17 1M 32 GPO4 VDD VSS GPO3 VDD VSS GPO2 VDD VSS GPO1 VSS RS2 Key2 10k CS2 16 15 1M RS1 Key1 10k SNS_SCK2 SNSK_SCK1 SNS_SCK1 MODE/GPO1 VSS_1 9 ADD0/GPO2 31 CS1 14 1M 30 VSS_2 10 VSS_3 11 VSS_4 12 1M Ai12559 19/51 Device operating modes QST108 4.6.2 General-purpose outputs I2C mode allows to drive up to 5 general-purpose outputs. These output pins are configured in output push pull mode 0 by default. Their state can be changed using the SET_GPIO_STATE I2C command. Figure 7. Optional LED schematic VUNREG R GPOn C (10 nF) Ai12570 4.6.3 IRQ pin The IRQ pin is an open drain output with an internal pull-up. It can be used to inform the Master device about any change in the key status. The IRQ line is pulled low every time the state of any of the enabled keys changes. This includes any change in the touch state of the key, a faulty key or a new calibration of one or more keys. The reported changes may then be accessed by the Master device by using the GET_KEY_STATE command. To improve communication response time, this signal suspends Low Power mode until the Master device has issued a communication with the QST device. 4.6.4 Communication packet The communication between the Master device and the QST108 (Slave) consists of two standard I2C frames. The first frame is sent by the Master device using the QST108 device address with the write bit set. The data bytes consist of the command byte which is eventually followed by the parameters and a checksum byte. The second one is sent by the Master device using the QST108 device address with the write bit reset. The QST108 completes the frame with data according to the command previously sent by the Master device. The device finishes the frame by sending a checksum byte for communication integrity verification. If the read frame is omitted, the command may not be taken into account. To initiate the communicate with the QST108, the Master device must send the GET_DEVICE_INFO command in order to unlock access to all the other commands. 20/51 QST108 Device operating modes 4.6.5 I2C address selection The QST108 slave address is programmable using the option resistors mapped on pins OPT2 to OPT4 (see Table 9). Table 9. IC address versus option resistor I2C Address ADD[6:3] ADD2 0 0 0 0 0101 1 1 1 1 0 0 1 1 0 1 0 1 0x2C 0x2D 0x2E 0x2F ADD1 0 0 1 1 ADD0 0 1 0 1 Hex value 0x28 0x29 0x2A 0x2B Option configuration OPT4 VSS VSS VSS VSS VDD VDD VDD VDD OPT3 VSS VSS VDD VDD VSS VSS VDD VDD OPT2 VSS VDD VSS VDD VSS VDD VSS VDD 4.7 Note: Supported commands Table 10 lists the supported IC commands and available arguments. For more information on the supported commands and I2C protocol, please refer to the QST standard communication protocol reference manual. Table 10. Supported commands I2C commands CALIBRATE_KEY (All keys) Write Read 0x98 ErrCode Forces the recalibration of all keys. ErrCode: Standard Error code (see Table 11) Description CALIBRATE_KEY (Single key) Write Read 0x9B KeyID Checksum ErrCode Forces the recalibration of a single key. KeyId: Binary-coded key number (see Table 14) ErrCode: Standard Error code (see Table 11) GET_DEBUG_INFO Write 0xF7 KeyID Checksum 0x0B KeyDbgState RefMSB RefLSB BCMSB BCLSB Checksum Returns the debug info of the single KeyID channel. KeyDbgState: Current Key Debug state (see Table 19) RefMSB: Reference Count MSB RefLSB: Reference Count LSB BCMSB: Burst Count MSB BCLSB: Burst Count LSB Read 21/51 Device operating modes Table 10. Supported commands (continued) I2C commands GET_DEVICE_INFO Write Description QST108 Read Returns the QST108 device version and ASCII-coded device name. This command must be sent first to enable the communication flow. 0x15 MainVers SubVers MainVers: Device main version NbSCkey NbMCkey SubVer: Device sub-version `Q' 'S' `T' `1' `0' `8' NbSCkey: 0x08 single-channel keys Checksum NbMCkey: 0x00 multi-channel keys Q S T 1 0 8: ASCII-coded device name 0x85 GET_KEY_ERROR Write Read 0xC4 0x10 KeyError1 KeyError2 ... KeyError8 CheckSum Returns the error information on each key. KeyErrorN: KeyError byte description (see Table 12) GET_KEY_STATE Write Read 0xC1 0x04 AllKeyState KeyError Checksum Returns the state of all keys. AllKeyState: Touched/untouched state for all 8 keys. Refer to Table 13: AllKeyState. KeyError: Refer to Table 12: KeyError byte description GET_PROTOCOL_VERSION Write Read 0x80 0x07 MainVers SubVer I2CSpeed Checksum Returns the QST108 protocol version. MainVers: Protocol main version SubVer: Protocol sub-version I2CSpeed: 0x00 (100 kHz maximum) RESET_DEVICE Write Read 0xFD ErrCode Restarts the device (options Read and Calibration) after reading the ErrCode (see Table 11). SET_DETECT_INTEGRATORS Write 0x03 0x04 0x00 DI EDI PosRecaII CheckSum Sets the detection, End Of Detection and Positive Recalibration Integrators for all keys. DI: Detection Integrator 1) 3) EDI: End of Detection Integrator 1) 3) PosRecaII: Positive Recalibration Integrator 1) 3) ErrCode: Standard Error code (see Table 11) Read ErrCode SET_GPIO_STATE Write Read 0x08 0x01 GPOState Checksum ErrCode Controls the state of the general-purpose outputs. GPOState: State of general-purpose outputs (see Table 16) ErrCode: Standard Error code (see Table 11) 22/51 QST108 Table 10. Supported commands (continued) I2C commands SET_KEY_ACTIVATION (see Note 4) Write Read 0x97 KeyActivation Checksum ErrCode Device operating modes Description Enables or disables a single key. KeyActivation: Byte containing the key number selection and requested state. ErrCode: Standard Error code (see Table 11) SET_KEY_GROUP 0x00 0x09 AKSGrpMode Key1Grp Key2Grp ...Key8Grp CheckSum ErrCode Defines the AKS groups for each key. AKSGrpMode: AKS mode selection of each group (see Table 17) KeynGrp: AKS group selection for key n (see Table 18) ErrCode: Standard Error code (see Table 11) Write Read SET_LOW_POWER_MODE Write Read 0x92 LowPowerMode Checksum ErrCode Selects standard or Low Power mode. LowPowerMode: Configure Low Power mode (see Table 15) ErrCode: Standard Error code (see Table 11) SET_MAX_ON_DURATION Write Read 0x8A MaxOnDuration Checksum ErrCode Sets the maximum detected ON time before triggering an automatic recalibration. MaxOnDuration: Time, in second (0 for infinite) ErrCode: Standard Error code (see Table 11) SET_SCKEY_PARAMETERS Write 0x01 0x04 0x00 DeTh EofDeTh PosRecalTh Checksum ErrCode Sets the Detection, End Of Detection and Positive Recalibration Thresholds for a single key. DeTh: Detection Threshold 1) 2) EofDeTh: End of Detection Threshold 1) 2) PosRecalTh: Positive Recalibration Threshold 1) 2) ErrCode: Standard Error code (see Table 11) Read Note: 1 2 3 4 See Section 6.6: Capacitive sensing characteristics on page 35 for default values. The value is a signed character (0x80...0x7F <=> -128 ... +128). The value is an unsigned number (0x01..0xFF <=> 1 ... 255). Enabling or disabling keys triggers a new calibration of all enabled keys. 23/51 Device operating modes QST108 Error codes Table 11 lists the I2C error codes. Table 11. ErrCode 0x01 0x83 0x85 0xA1 0xA3 0xE0 No Error Command not supported Parameter not supported Parity Error Checksum Error Initialization process (GET_FIRMWARE_INFO command not received) ErrCode Description KeyError byte description Table 12. Bit 7 Key State KeyError byte description Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 Bit 1 Key error codes Bit 0 Key state (Bit 7) When set to `1', the corresponding key is touched. This bit is always cleared for the GET_KEY_STATE command. Key error codes (Bits 2:0) When answering the GET_KEY_STATE command, the key error code corresponds to the error codes of all the keys ORed toghether. When answering the GET_KEY_ERROR command, each key error code describes the errors of one defined key. Bit 0: When set to `1', calibration in progress Bit 1: When set to `1', maximum count reached Bit 2: When set to `1', minimum count not reached All key state description Table 13. Bit 7 AllKeyState Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Key 8 State Key 7 State Key 6 State Key 5 State Key 4 State Key 3 State Key 2 State Key 1 State Key n state When set to `1', the corresponding key is touched. 24/51 QST108 Device operating modes Key activation description Table 14. Bit 7 Key Activation KeyActivation Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 Bit 2 Bit 1 Bit 0 Key ID (binary coded) Key activation (Bit 7) 0: Key disabled 1: Key enabled Key identifier (Bits 3:0) 0000: All keys 0001: Key 1 0010: Key 2 0011: Key 3 0100: Key 4 0101: Key 5 0110: Key 6 0111: Key 7 1000: Key 8 Low power mode description Table 15. Bit 7 0 SetLowPower Bit 6 Free Run in Detect Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Sleep Duration Factor Free Run in Detect (Bit 6) 0: Low Power mode is always enabled, whatever the state of the keys. 1: Low Power mode is automatically suspended when any key is in Detect state. Low Power mode is automatically resumed when no key is in Detect state. Sleep Duration Factor (Bits 5 to 0) 0x00 or 0x1A to 0x3E: Low power mode is disabled. 0x01 to 0x19: Low Power mode. The sleep duration is `Sleep Duration Factor' x 20 milliseconds (20 ms to 500 ms) 0x3F: Deep Sleep mode is entered immediately. A reset or any I2C communication can be used to exit Deep Sleep mode. Note: When the device is in Sleep or Deep Sleep, any I2C bus activity will wake-up the device. The I2C QST device address is not acknowledged but forces the QST device to exit from Low Power mode. The Master device will have to repeat the command to ensure that it is taken in account. 25/51 Device operating modes QST108 GPO state description Table 16. Bit 7 0 GPOState Bit 6 0 Bit 5 0 Bit 4 GPO 5 state Bit 3 GPO 4 state Bit 2 GPO 3 state Bit 1 GPO 2 state Bit 0 GPO 1 state GPOState Defines the state of the selected general-purpose output pin. For more information, see Section 4.6.2: General-purpose outputs on page 20. 0: GPO state is `0' 1: GPO state is `1' AKS group mode description Table 17. Bit 7 AKSGrp8 Mode AKSGrpnMode Bit 6 AKSGrp7 Mode Bit 5 AKSGrp6 Mode Bit 4 AKSGrp5 Mode Bit 3 AKSGrp4 Mode Bit 2 AKSGrp3 Mode Bit 1 AKSGrp2 Mode Bit 0 AKSGrp1 Mode AKSGrpnMode Defines the type of AKS for the Group n: 0: Locking AKS: First key pressed within the group locks out all other keys. 1: Unlocking AKS: Most heavily pressed key (highest signal level) is selected over all other keys in the group. AKS group selection description Table 18. Bit 7 Grp8 KeynGrp Bit 6 Grp7 Bit 5 Grp6 Bit 4 Grp5 Bit 3 Grp4 Bit 2 Grp3 Bit 1 Grp2 Bit 0 Grp1 Grpx The selected key is a member of AKS Group x. Key debug state description Table 19. KeyDbgState Description On-going calibration Key released Key touched Key in error Key calibration filter triggered (PosRecalI) Key detection filter triggered (DI) Key end of detection filter triggered (EDI) Value 0x01 0x02 0x04 0x08 0x11 0x14 0x24 26/51 QST108 Design guidelines 5 5.1 Design guidelines CS sense capacitor The CS sense capacitors accumulate the charge from the key electrodes and determine sensitivity. Higher values of CS make the corresponding sensing channel more sensitive. The values of CS can differ for each channel, permitting differences in sensitivity from key to key or to balance unequal sensitivities. Unequal sensitivities can occur due to key size and placement differences and stray wiring capacitances. More stray capacitance on a sense trace will desensitize the corresponding key. Increasing the CS for that key will compensate for the loss of sensitivity. The CS capacitors can be virtually any plastic film or low- to medium-K ceramic capacitor. The normal CS range is 1nF to 50nF depending on the sensitivity required: larger values of CS require better quality to ensure reliable sensing. In certain circumstances the normal CS range may be exceeded. Acceptable capacitor types for most uses include PPS film, polypropylene film, and NP0 and X5R / X7R ceramics. Lower grades than X5R or X7R are not recommended. 5.2 Sensitivity tuning Sensitivity can be altered to suit various applications and situations on a channel-bychannel basis. The easiest and most direct way to impact sensitivity is to alter the value of each CS: more CS yields higher sensitivity. Each channel has its own CS value and can therefore be independently adjusted. 5.2.1 Increasing sensitivity Sensitivity can also be increased by using larger electrode areas, reducing panel thickness, or using a panel material with a higher dielectric constant. 5.2.2 Decreasing sensitivity In some cases the circuit may be too sensitive. Gain can be lowered further by a number of strategies: making the electrode smaller making the electrode into a sparse mesh using a high space-to-conductor ratio decreasing the CS capacitors 5.2.3 Key balance A number of factors can cause sensitivity imbalances. Notably, SNS wiring to electrodes can have differing stray amounts of capacitance to ground. Increasing load capacitance will cause a decrease in gain. Key size differences, and proximity to other metal surfaces can also impact gain. The keys may thus require "balancing" to achieve similar sensitivity levels. This can be best accomplished by trimming the values of the CS capacitors to achieve equilibrium. The RS resistors have no effect on sensitivity and should not be altered. Load capacitances to ground can also be added to overly sensitive channels to reduce their gain. These should be in the order of a few picofarads. 27/51 Design guidelines QST108 5.3 Power supply If the power supply fluctuates slowly with temperature, the QST device compensates automatically for these changes with only minor changes in sensitivity. However, if the supply voltage drifts or shifts quickly, the drift compensation mechanism is not able to keep up, causing sensitivity anomalies or false detections. The power supply should be locally regulated, using a three-terminal regulator. If the supply is shared with another electronic system, care should be taken to ensure that the supply is free of digital spikes, sags and surges which can cause adverse effects. It is not recommended to include a series inductor in the power supply to the QST device. For proper operation, a 0.1 F or greater bypass capacitor must be used between VDD and VSS. The bypass capacitor should be routed with very short tracks to the device's VDD and VSS pins. The PCB should, if possible, include a copper pour under and around the device, but not extensively under the SNS lines. 5.4 ESD protection In normal environmental conditions, only one series resistor is required for ESD suppression. A 10 kOhm RS resistor in series with the sense trace is sufficient in most cases. The dielectric panel (glass or plastic) usually provides a high degree of isolation to prevent ESD discharge from reaching the circuit. RS should be placed close to the chip. If the CX load is high, RS can prevent total charge and transfer and as a result gain can deteriorate. If a reduction in RS increases gain noticeably, the lower value should be used. Conversely, increasing the RS can result in added ESD and EMC benefits, provided that the increase does not decrease sensitivity. 5.5 Crosstalk precautions Adjacent sense traces might require intervening ground traces in order to reduce capacitive cross bleed if high sensitivity is required or high values of delta-CX are anticipated (for example, from direct human touch to an electrode connection). In normal touch applications behind plastic panels, this is rarely a problem regardless of how the electrodes are wired. Higher values of RS will make crosstalk problems worse; try to keep RS to 22 kOhm or less if possible. In general try to keep the QST device close to the electrodes and reduce the adjacency of the sense wiring to ground planes and other signal traces; this will reduce the Cx load, reduce interference effects, and increase signal gain. The one and only valid reason to run ground near SNS traces is to provide crosstalk isolation between traces, and then only on an as-needed basis. 5.6 PCB layout and construction The PCB traces, wiring, and any components associated with or in contact with either SNS pin will become touch sensitive and should be treated with caution to limit the touch area to the desired location. Multiple touch electrodes connected to any sensing channel can be used, for example, to create control surfaces on both sides of an object. 28/51 QST108 Design guidelines It is important to limit the amount of stray capacitance on the SNS terminals, for example by minimizing trace lengths and widths to allow for higher gain without requiring higher values of CS. Under heavy delta-CX loading of one key, cross coupling to another key's trace can cause the other key to trigger. Therefore, electrode traces from adjacent keys should not be run close to each other over long runs in order to minimize cross-coupling if large values of delta-CX are expected, for example when an electrode is directly touched. This is not a problem when the electrodes are working through a plastic panel with normal touch sensitivity. For additional information on PCB layout and construction, please contact your local ST Sales Office for a list of available application notes. 29/51 Electrical characteristics QST108 6 6.1 Electrical characteristics Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 5 V (for the 4.5V VDD 5.5 V voltage range) and VDD = 3.3 V (for the 3.0 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 8. Figure 8. Pin loading conditions Output pin 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 9. Figure 9. Pin input voltage Input pin VIN 30/51 QST108 Electrical characteristics 6.2 Absolute maximum ratings Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 20. Symbol TSTG TJ Thermal characteristics Ratings Storage temperature range Maximum junction temperature Value -65 to +150 C Unit Table 21. Symbol VDD - VSS VIN Voltage characteristics Ratings Supply voltage Input voltage on any pin (1)(2) Maximum value 7.0 VSS-0.3 to VDD+0.3 Unit V 1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset is generated or an unexpected change of the I/O configuration occurs. To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k for RESET, 10k for I/Os). 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN Symbol IVDD IVSS Current characteristics Ratings Total current into VDD power lines (source)(1) Total current out of VSS ground lines Output current sunk by RESET pin (sink)(1) Maximum value 75 150 20 40 - 25 5 5 20 mA Unit IIO Output current sunk by output pin Output current source by output pin IINJ(PIN)(2)(3) IINJ(PIN)(2) Injected current on RESET pin Injected current output pin Total injected current (sum of all I/O and control pins) 1. All power (VDD) and ground (VSS) lines must always be connected to the external supply. 2. IINJ(PIN) must never be exceeded. This is implicitly ensured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN Electrical characteristics QST108 6.3 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. 6.3.1 Functional EMS (electro magnetic susceptibility) The product is stressed by two electro magnetic events until a failure occurs: ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. Table 23. Symbol VFESD Functional EMS Parameter Voltage limits to be applied on any I/O pin to induce a functional disturbance Fast transient voltage burst limits to be applied through 100pF on VDD and VDD pins to induce a functional disturbance Conditions VDD=5V, TA=+25C, complies with IEC 1000-4-2 VDD=5V, TA=+25C complies with IEC 1000-4-4 Level/ Class 3B VFFTB 4A 6.3.2 Electro magnetic interference (EMI) The product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin. Table 24. Symbol EM emissions Parameter Conditions Monitored Frequency Band 0.1 MHz to 30 MHz fDEVICE = 4 MHz (1) Unit 20 20 13 2.5 dBV SEMI Peak level VDD=5V, TA=+25C, complies with SAE J 1752/3 30 MHz to 130 MHz 130 MHz to 1 GHz SAE EMI Level 1. Data based on characterization results, not tested in production. 32/51 QST108 Electrical characteristics 6.3.3 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. Electro-static discharge (ESD) Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models can be simulated: Human Body Model and Charge Device Model. These tests comply with JESD22-A114A/A115A specifications. Table 25. Symbol VESD(HBM) VESD(CDM) Absolute maximum ratings Ratings Electro-static discharge voltage (Human Body Model) Electro-static discharge voltage (Charge Device Model) Conditions TA=+25C TA=+25C Maximum value (1) 4000 500 Unit V V 1. Data based on characterization results, not tested in production. Static and dynamic latch-up LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each I/O pin) are performed on each sample. This test complies with EIA/JESD 78 IC latch-up specifications. DLU: Electro-Static Discharges (one positive then one negative test) are applied to each pin of 3 samples when the MCU is running to assess the latch-up performance in Dynamic mode. Power supplies are set to the typical values and the component is put in Reset mode. This test complies with IEC1000-4-2 and SAEJ1752/3 specifications. For more details, refer to the application note AN1181. Table 26. Symbol LU DLU Electrical sensitivities Parameter Static latch-up class Dynamic latch-up class TA=+125C VDD=5.5V, fDEVICE = 4MHz, TA=+25C Conditions Class (1) A A 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). 33/51 Electrical characteristics QST108 6.4 Operating conditions Table 27. Symbol VDD TA Operating supply voltage Operating temperature Operating conditions Feature Value 2.4 to 5.5 -40 to +85 Unit V C 6.5 Supply current characteristics Table 28. Symbol Supply current characteristics Parameter Conditions VDD = 2.4 V Min. Typ. (1) 1.71 2.17 3.35 276 389 637 108 144 246 5 A A A mA Max. Unit Average suppy current IDD (FR) Free Run mode VDD = 3.3 V VDD = 5 V IDD Average suppy current (Sleep 100ms Sleep mode 100ms) IDD Average suppy current (Sleep 500ms Sleep mode 500ms) IDD Deep Sleep Average suppy current Deep Sleep mode VDD = 2.4 V VDD = 3.3 V VDD = 5 V VDD = 2.4 V VDD = 3.3 V VDD = 5 V 1. The results are based on CS = 2.7nF and CX = 12.5pF Figure 10. IDD Sleep mode current characteristics 34/51 QST108 Electrical characteristics 6.6 Capacitive sensing characteristics Table 29. Symbol CS CX CT RS Sense capacitor Equivalent electrode capacitor Equivalent touch capacitor Serial resistor 5 10 22 External sensing components Parameter Min. Typ. Max. 100 100 Unit nF pF pF kOhm Table 30. Symbol tCAL tSetup DI DeTh EDI EofDeTh PosRecalI Capacitive sensing parameters Parameter Calibration duration Setup duration Detection integrator Detection threshold End of detection integrator End of detection threshold Positive recalibration integrator Positive recalibration threshold 1 -128 1 -128 1 1 1 0.1 0.1 0.1 0.1 0 0 0 0 20 100 2 -10 2 -6 2 15 Infinite 1 1 0.2 0.2 10 10 2 10 255 -1 255 -1 255 127 255 25.5 25.5 25.5 25.5 255 255 255 255 2000 Counts Min. Default Max. 2 Unit s ms Samples Counts Samples Counts Samples Counts s s/level s/level s/level s/level PosRecalTh MaxOnDuration Max on-duration delay PosDiffDrift NegDiffDrift PosComDrift NegComDrift PosDriftI NegDriftI ComFact DiffFact BurstCount Positive differential drift compensation rate Negative differential drift compensation rate Positive common drift compensation rate Negative common drift compensation rate Positive drift integrator Negative drift integrator Common time step factor Differential time step factor Burst length 35/51 Electrical characteristics QST108 6.7 6.7.1 KOUTn/OPTn/GPOn pin characteristics General characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. Table 31. Symbol VIL VIH VHys IL CIO General characteristics Parameter Input low level voltage (1) Input high level voltage (1) Conditions Min. VSS -0.3 0.7x VDD Typ. Max. 0.3x VDD VDD + 0.3 Unit V mV Schmitt trigger voltage hysteresis(2) Input leakage current I/O pin capacitance CL = 50 pF Between 10% and 90% VSS VIN VDD 400 1 5 25 A pF tf(IO)out Output high to low level fall time (2) tr(IO)out Output low to high level rise time (2) ns 25 1. Not tested in production, guaranteed by characterization. 2. Data based on validation/design results. 6.7.2 Output pin characteristics Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Table 32. Symbol VOL(1) Output pin current Parameter Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time (Figure 16) Output high level voltage for an I/O pin when 4 pins are sourced at same time (Figure 21) Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time Conditions IIO = +20mA VDD = 5V IIO = +8mA IIO = -5mA IIO = -2mA VDD = 3.3V IIO = +8mA IIO = -2mA IIO = +8mA IIO = -2mA VDD-0.9 VDD-0.8 0.6 VDD-1.5 VDD-0.8 0.5 V Min. Max. 1.3 0.75 Unit VOH(2) VOL(1)(3) Output high level voltage for an I/O pin VOH(2)(3) when 4 pins are sourced at same time (Figure 19) VOL(1)(3) VOH(2)(3) Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time Output high level voltage for an I/O pin when 4 pins are sourced at same time 1. The IIO current sunk must always respect the absolute maximum rating specified in Table 22 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Table 22 and the sum of IIO (output and RESET pins) must not exceed IVDD.. 3. Not tested in production, based on characterization results. 36/51 VDD = 2.4V QST108 Electrical characteristics Figure 11. Typical VOL at VDD = 2.4 V VOL vs Iload @ VDD = 2.4 V HS pins Figure 12. Typical VOL vs VDD at Iload = 2 mA VOLvs VDD @Iload=2 mA HS Pins 1200 1000 800 -40C 25C 85C 125C 120 110 100 VOL[mV] -40C 25C 85C 125C 90 80 70 60 50 40 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 VOL [V] 600 400 200 0 0 2 4 6 8 10 12 14 16 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 VDD [V] Iload [mA] Figure 13. Typical VOL at VDD = 3 V VOLvs Iload @ VDD = 3 V HS pins Figure 14. Typical VOL vs VDD at Iload = 8 mA VOL vs VDD@Iload = 8 mA HS Pins 1600 1400 1200 -40C 25C 85C 125C 540 490 440 VOL[mV] -40C 25C 85C 125C VOL [V] 1000 800 600 400 200 0 0 2 4 6 8 10 12 14 16 18 20 390 340 290 240 190 140 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 V DD [V] Iload [mA] Figure 15. Typical VOL at VDD = 5 V VOL vs Iload @ VDD = 5 V HS pins Figure 16. Typical VOL vs VDD at Iload = 12 mA VOL vs VDD @Iload = 12 mA HS Pins 900 800 700 600 -40C 25C 85C 125C 1040 940 840 740 VOL[mV] -40C 25C 85C 125C VOL [V] 500 400 300 200 100 0 0 2 4 6 8 10 12 14 16 18 20 640 540 440 340 240 140 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 V DD [V] Iload [mA] Figure 17. Typical VDD-VOH vs. Iload at VDD = 2.4 V VDD-VOH vs Iload @ VDD = 2.4 V HS Pins Figure 18. Typical VDD-VOH vs. VDD at Iload = 2 mA VDD-VOH vs VDD @Iload = 2 mA HS Pins 800 700 600 VDD-VOH [mV] 500 400 300 200 100 0 -40C 25C 85C 125C 800 700 600 VDD-VOH [mV] 500 400 300 200 100 0 -40C 25C 85C 125C 2. 8 3. 6 4 4. 4 2. 4 3. 2 4. 8 5. 2 2 Iload [mA] 4 VDD [V] 5. 6 37/51 Electrical characteristics Figure 19. Typical VDD-VOH vs. Iload at VDD = 3 V VDD-VOH vs Iload @ VDD = 3 V HS Pins QST108 Figure 20. Typical VDD-VOH vs. VDD at Iload = 4 mA VDD-VOH vs VDD @Iload = 4 mA HS Pins 1800 1600 1400 VDD-VOH [mV] 1200 1000 800 600 400 200 0 -40C 25C 85C 125C 1800 1600 1400 VDD -VOH [mV] 1200 1000 800 600 400 200 0 3 2. 6 4. 6 3. 4 3. 8 4. 2 5 -40C 25C 85C 125C 0 2 Iload[mA] 4 6 VDD [V] Figure 21. Typical VDD-VOH vs. Iload at VDD = 5 V V DD-V OH vs Iload @ V DD = 5 V HS Pins 4500 4000 3500 VDD-VOH [mV] 3000 2500 2000 1500 1000 500 0 -40C 25C 85C 125C 0 2 4 6 8 10 12 14 Iload[mA] 38/51 5. 4 QST108 Electrical characteristics 6.8 RESET pin TA = -40C to 125C, unless otherwise specified. Table 33. Symbol VIL VIH Vhys VOL RON tw(RSTL)out th(RSTL)in tg(RSTL)in RESET pin characteristics Parameter Input low level voltage Input high level voltage Schmitt trigger voltage hysteresis(1) Output low level voltage(2) Pull-up equivalent resistor(3) Generated reset pulse duration External reset pulse hold time(4) Filtered glitch duration VDD = 5V VIN = VSS IIO = +2mA VDD = 5V VDD = 3V 30 Conditions Min. VSS - 0.3 0.7 x VDD 2 200 50 90(1) 90(1) 20 200 70 k s s ns Typ. Max. 0.3x VDD VDD + 0.3 V mV Unit V Internal reset sources 1. Data based on characterization results, not tested in production. 2. The IIO current sunk must always respect the absolute maximum rating specified in Table 22: Current characteristics on page 31 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 3. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between VILmax and VDD. 4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on RESET pin with a duration below th(RSTL)in can be ignored. 39/51 Electrical characteristics QST108 6.9 I2C control interface Subject to general operating conditions for VDD, and TA unless otherwise specified. The QST108 I2C interface meets the requirements of the Standard I2C communication protocol described in the following table with the restriction mentioned below: Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 34. Symbol tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) tsu(STO) Cb SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time START condition hold time Repeated START condition setup time STOP condition setup time Capacitive load for each bus line 4.0 4.7 4.0 4.7 400 IC characteristics (100 kHz speed) Parameter Min. (1) 4.7 4.0 250 0 (2) 1000 ns 300 s s s pF Max. (1) Unit s ns tw(STO:STA) STOP to START condition time (bus free) 1. Data based on standard I2C protocol requirement, not tested in production. 2. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of the SCL signal. Table 35. Symbol tW(IRQ) RIRQ IRQ specific pin characteristics (1) Parameter IRQ pulse width IRQ internal pull-up (2) VDD = 5V VDD = 3V Conditions Min. 10 100 120 300 Typ. Max. 15 140 k Unit s 1. For additional pin parameters, please use the pin description in Section 6.7: KOUTn/OPTn/GPOn pin characteristics on page 36. 2. The IRQ pull-up equivalent resistor is based on a resistive transistor. 40/51 QST108 Electrical characteristics Figure 22. Typical application with I2C bus and timing diagram VDD 4.7k I 2C VDD 4.7k 100 100 SDA SCL BUS QST device REPEATED START START tsu(STA) SDA tw(STO:STA) START tf(SDA) SCL tr(SDA) tsu(SDA) th(SDA) STOP th(STA) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) tsu(STO) 41/51 Package mechanical data QST108 7 Package mechanical data Figure 23. 32-pin low profile quad flat package (7x7) outline Seating plane C A A2 A1 ccc C D D1 D3 24 17 16 A1 L L1 K c 0.25 mm Gage plane b 25 E3 E1 E 32 Pin 1 identification 9 1 8 e 5V_ME 42/51 QST108 Table 36. Dim. Min. A A1 A2 b c D D1 D3 E E1 E3 e L L1 K ccc 0.0 0.450 8.800 6.800 0.050 1.350 0.300 0.090 8.800 6.800 9.000 7.000 5.600 9.000 7.000 5.600 0.800 0.600 1.000 3.5 Tolerance (mm) 0.10 7.0 0.0 0.750 0.0177 9.200 7.200 0.3465 0.2677 1.400 0.370 Typ. Max. 1.600 0.150 1.450 0.450 0.200 9.200 7.200 0.0020 0.0531 0.0118 0.0035 0.3465 0.2677 Min. Package mechanical data 32-pin low profile quad flat package mechanical data mm Typ. inches(1) Max. 0.0630 0.0059 0.0551 0.0146 0.3543 0.2756 0.2205 0.3543 0.2756 0.2205 0.0315 0.0236 0.0394 3.5 Tolerance (inches) 0.0039 7.0 0.0295 0.3622 0.2835 0.0571 0.0177 0.0079 0.3622 0.2835 1. Values in inches are converted from mm and rounded to 4 decimal digits. 43/51 Package mechanical data Figure 24. 32-pin LQFP32 (7x7 mm) recommended footprint 0.80 QST108 1.20 9 8 16 17 0.50 0.30 7.30 9.70 6.10 7.30 1 32 25 1.20 24 6.10 9.70 All dimensions are in millimeters. Ai15211 44/51 QST108 Package mechanical data 7.1 Soldering information In accordance with the RoHS European directive, all STMicroelectronics packages have been converted to lead-free technology, named ECOPACKTM. ECOPACKTM packages are qualified according to the JEDEC STD-020C compliant soldering profile. Detailed information on the STMicroelectronics ECOPACKTM transition program is available on www.st.com/stonline/leadfree/, with specific technical Application notes covering the main technical aspects related to lead-free conversion (AN2033, AN2034, AN2035, and AN2036). Backward and forward compatibility The main difference between Pb and Pb-free soldering process is the temperature range. ECOPACKTM LQFP, SDIP, SO and DFN8 packages are fully compatible with Lead (Pb) containing soldering process (see application note AN2034). LQFP, SDIP and SO Pb-packages are compatible with Lead-free soldering process, nevertheless it's the customer's duty to verify that the Pb-packages maximum temperature (mentioned on the Inner box label) is compatible with their Lead-free soldering temperature. Soldering Compatibility (wave and reflow soldering process Plating material devices Sn (pure Tin) Sn (pure Tin) NiPdAu (Nickel-palladium-Gold) Pb solder paste Pb-free solder paste (1) Yes Yes Yes Yes Yes Yes Table 37. Package SDIP & PDIP DFN8 TQFP and SO 1. Assemblers must verify that the Pb-package maximum temperature (mentioned on the Inner box label) is compatible with their Lead-free soldering process. 45/51 Part numbering QST108 8 Part numbering Table 38. Example: Device type QST = Capacitive touch sensor Device sub-family 1: 5: 6: 11: 15: 16: QTouch (3 to 5 V) QMatrix (3 to 5 V) QSlide/QWheel (3 to 5 V) QTouch (1.8 to 3.6 V) QMatrix (1.8 to 3.6 V) QSlide/QWheel (1.8 to 3.6 V) Ordering information scheme QST 1 08 K T 6 Channel count Number of channels Pin count A: Y: K: 8 pins 16 pins 32 pins S: 44 pins C: 48 pins M: 80 pins Package B: H: M: N: T: U: DIP (dual in-line) BGA (ball grid array) SO (small outline) TSSOP (thin-shrink small outline package) LQFP (thin quad flat) QFN (dual quad flat no lead) Temperature range 0: 1: 5: +25C 0 to +70C -10C to +85C 6: -40C to +85C 7: -40C to +105C 9: -40C to + 125C For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. 46/51 QST108 Device revision information 9 9.1 Device revision information Device revision identification The marking on the right side of the second line (Line B) of the package top face identifies the device revision. Figure 25. Device revision identification (TQFP package) A QST108 QRG D B F01 E C F G H a J I K Table 39. Device revision identification Marking F00 F01 Device revision V 2.1 V 2.3 The device revision can also be obtained using the GET_DEVICE_INFO I2C command. For more information, refer to Section 4.9: Supported commands on page 16. 9.2 Device revision history This section identifies the device deviations from the present specification for each device revision. 9.2.1 Revision 2.1 Engineering samples. For more information regarding this revision, please contact your local ST sales office. 47/51 Device revision information QST108 9.2.2 Revision 2.3 When the device enters Low Power mode, an additional sleep time is inserted after each burst, instead of once after every complete burst cycle. As a result, if only one burst is required, the sleep duration during Low Power mode is doubled. And if two bursts are required, the sleep duration is tripled. In Standalone mode, the 100ms sleep duration low power becomes either a 200ms or 300ms sleep duration depending on the number of bursts required. In I2C mode, it is required to program a sleep duration for one half or a third of the desired sleep duration depending on the number of bursts required. GET_PROTOCOL_VERSION returns 0x01 as I2CSpeed byte when it should return 0x00 (maximum speed is 100 kHz). If a command is sent with an incorrect parity bit, the device reports an unsupported command instead of a parity error. In I2C mode, it is recommended to set the fast positive recalibration threshold to 5 using the SET_SCKEY_PARAMETERS command in order to ensure a reliable behavior on low sensitivity keys. AKS should be always enabled in BCD mode. The AKS pull-up option resistor should be connected to pin KOUT2. 48/51 QST108 Revision history 10 Revision history Table 40. Date 8-Jun-2007 15-Jun-2007 Document revision history Revision 1 2 Initial release. Datasheet status changed to Preliminary Data. Removed Beeper function. Changed LED output pins to GPO pins. Updated pin names and functions in Section 2: Pin description on page 5 and added Figure 2: QTouchTM measuring circuitry on page 7. Changed order of chapters in Section 3 for better comprehension. Removed Simplified independent output mode from Section 4: Device operating modes on page 11. Independent output mode renamed Stand-alone mode. Added Section 4.2: Reset and power-up on page 11 and removed Power supply option chapter from Section 4.4.2: Option descriptions on page 14. Updated Table 6: Max On-Duration (MOD) truth table on page 14 and Table 7: Output mode (OM) truth table on page 15. Updated Figure 3: Stand-alone mode typical schematic on page 13 and Figure 4: I2C mode typical schematic on page 16. Updated Table 9: IC address versus option resistor on page 18. Added Figure 5: Optional LED schematic on page 17. Updated Section 4.5: I2C mode on page 15. Added Section 5.2.3: Key balance on page 25. Updated Section 6.4: Supply current characteristics on page 31. Added Section 6.5: Capacitive sensing characteristics on page 32. and Section 6.7: RESET pin on page 36. Updated Table 30: IC characteristics on page 37. Document status promoted from Preliminary Data to Datasheet. Added ECOPACK(R) information. Updated CX value in Figure 2: QTouchTM measuring circuitry on page 7. Added Caution note in Section 3.10: Drift compensation on page 11. Added Section 4.3: Low power mode on page 13. Updated hex values in Table 9: IC address versus option resistor on page 21. Updated Table 28: Supply current characteristics on page 34, Table 30: Capacitive sensing parameters on page 35 and added Figure 10: IDD Sleep mode current characteristics on page 34. Added Table 35: IRQ specific pin characteristics on page 40. Added Section 9: Device revision information on page 47. Changes 26-Sep-2007 3 22-Nov-2007 4 49/51 Revision history Table 40. Date QST108 Document revision history (continued) Revision Changes Changed datasheet status to Not for new design. Updated Figure 2: QTouchTM measuring circuitry to add RS sense resistor.* Updated Section 3.5: Detection integrator filter on page 9 and added Figure 3: Detection signals on page 10. Added Figure 4: Drift compensation example on page 12. GET_KEY_ERROR and GET_KEY_STATE read values updated in Table 10: Supported commands on page 21 and updated note 3. Updated bit values for Key activation description on page 25. Added Section 6.3: EMC characteristics on page 32. Updated Table 30: Capacitive sensing parameters on page 35. Added Figure 24: 32-pin LQFP32 (7x7 mm) recommended footprint on page 44. Added Section 7.1: Soldering information on page 45. Added Section 9.2.2: Revision 2.3 on page 48. 11-Jul-2008 5 50/51 QST108 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 51/51 |
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